WM8786 Datasheet, PDF (9/27 Pages) Wolfson Microelectronics plc – 24-Bit, 192kHz Stereo ADC

AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
WM8786
BCLK
LRCLK
DOUT
t_BCY
t_DD
t_LRH
t_LRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25°C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
SYMBOL
tBCY
tLRSU
tLRH
tDD
MIN
TYP
MAX
UNIT
25
ns
10
ns
10
ns
0
11
ns
Rev 4.4
9