WM8786 Datasheet, PDF (20/27 Pages) Wolfson Microelectronics plc – 24-Bit, 192kHz Stereo ADC

WM8786
LRCLK
1/fs
LEFT
CHANNEL
RIGHT
CHANNEL
BCLK
DOUT
1 BCLK
123
MSB
n-2 n-1 n
LSB
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 21 I²S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on the 2^nd rising edge of BCLK following a
rising edge of LRC. Right channel data immediately follows left channel data. Depending on word
length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the
right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 22. In device
slave mode, shown in Figure 23 it is possible to use any length of frame pulse less than 1/fs,
providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising
edge of the next frame pulse.
LRCLK
BCLK
DACDAT /
ADCDAT
1/fs
1 BCLK
LEFT CHANNEL
RIGHT CHANNEL
123
n-2 n-1 n 1 2 3
MSB
LSB
Input Word Length (WL)
n-2 n-1 n
Figure 22 DSP/PCM Mode Audio Interface (mode A, Master)
LRCLK
BCLK
DACDAT /
ADCDAT
1 BCLK
1/fs
falling edge can occur anywhere in this area
LEFT CHANNEL
RIGHT CHANNEL
123
n-2 n-1 n 1 2 3
MSB
LSB
Input Word Length (WL)
n-2 n-1 n
Figure 23 DSP/PCM Mode Audio Interface (mode A, Slave)
1 BCLK
20
Rev 4.4