EP9302 Datasheet, PDF (9/42 Pages) Cirrus Logic – High-speed ARM9 System-on-chip Processor with MaverickCrunch

EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
PLL and Clocking
The Processor and the Peripheral Clocks operate from a
single 14.7456 MHz crystal.
The Real Time Clock operates from a 32.768 KHz
external oscillator.
Table J. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Name - Description
XTALI
XTALO
VDD_PLL
GND_PLL
Main Oscillator Input
Main Oscillator Output
Main Oscillator Power
Main Oscillator Ground
Timers
The Watchdog Timer ensures proper operation by
requiring periodic attention to prevent a reset-on-time-
out.
Two 16-bit timers operate as free running down-counters
or as periodic timers for fixed interval interrupts and have
a range of 0.03 ms to 4.27 seconds.
One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03 µs to 73.3 hours.
One 40-bit debug timer, plus 6-bit prescale counter, has a
range of 1.0 µs to 12.7 days.
Interrupt Controller
The interrupt controller allows up to 54 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. GPIO pins programmed as
interrupts may be programmed as active high level
sensitive, active low level sensitive, rising edge triggered,
falling edge triggered, or combined rising/falling edge
triggered.
• Supports 54 interrupts from a variety of sources (such
as UARTs, GPIO and ADC)
• Routes interrupt sources to either the ARM920T’s
IRQ or FIQ (Fast IRQ) inputs
• Three dedicated off-chip interrupt lines operate as
active high level sensitive interrupts
• Any of the 19 GPIO lines maybe configured to
generate interrupts
• Software supported priority mask for all FIQs and
IRQs
Table K. External Interrupt Controller Pin Assignment
Pin Mnemonic
Pin Name - Description
INT[3] and INT[1:0]
External Interrupts 2, 1, 0
Note: INT[2] is not bonded out.
Dual LED Drivers
Two pins are assigned specifically to drive external
LEDs.
Table L. Dual LED Pin Assignments
Pin Mnemonic
Pin Name -
Description
Alternative Usage
GRLED
REDLED
Green LED
Red LED
General Purpose I/O
General Purpose I/O
General Purpose Input/Output (GPIO)
The 16 EGPIO and the 3 FGPIO pins may each be
configured individually as an output, an input, or an
interrupt input.
There are 10 pins that may alternatively be used as input,
output, or open-drain pins, but do not support interrupts.
These pins are:
• Ethernet MDIO
• Both LED Outputs
• EEPROM Clock and Data
• HGPIO[5:2]
• CGPIO[0]
6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 3 Interrupt Lines
2 pins may alternatively be used as outputs only:
• RTSn
• ARSTn
Table M. General Purpose Input/Output Pin Assignment
Pin Mnemonic
Pin Name - Description
EGPIO[15:0]
FGPIO[3:1]
Expanded General Purpose Input / Output
Pins with Interrupts
Expanded General Purpose Input / Output
Pins with Interrupts
DS653PP3
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