EP9302 Datasheet, PDF (7/42 Pages) Cirrus Logic – High-speed ARM9 System-on-chip Processor with MaverickCrunch

EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
• Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
• Interfaces to an off-chip PHY through industry-
standard Media-independent Interface (MII)
Table C. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
Pin Description
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
Management Data Clock
Management Data I / O
Receive Clock
Receive Data
Receive Data Valid
Receive Data Error
Transmit Clock
Transmit Data
Transmit Enable
Transmit Error
Carrier Sense
Collision Detect
Serial Interfaces (SPI, I²S, and AC ’97)
The Serial Peripheral Interface (SPI) port can be
configured as a master or a slave, supporting the
National Semiconductor^®, Motorola^®, and Texas
Instruments^® signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I²S port
supports stereo 24-bit audio.
These ports are multiplexed so that the I²S port will take
over either the AC'97 pins or the SPI pins.
• Normal Mode: One SPI Port and one AC’97 Port
• I²S on SSP Mode: One AC’97 Port and one I²S Port
• I²S on AC’97 Mode: One SPI Port and one I²S Port
Note: I²S may not be output on AC’97 and SSP ports at the
same time.
Table D. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I²S on SSP
Mode
Pin
Description
Pin Description
I²S on AC'97
Mode
Pin Description
SCLK1 SPI Bit Clock I2S Serial Clock SPI Bit Clock
SFRM1 SPI Frame Clock I2S Frame Clock SPI Frame Clock
SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output SPI Serial Output
(No I2S Master
Clock)
ARSTn AC'97 Reset AC'97 Reset
I2S Master Clock
ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial Output I2S Serial Output
12-bit Analog-to-digital Converter (ADC)
The ADC block consists of a 12-bit analog-to-digital
converter with a analog input multiplexer. The multiplexer
can select to measure battery voltage and other
miscellaneous voltages on the external measurement
pins. Features include:
• 5 external pins for ADC measurement
• Measurement pin input range: 0 to 3.3 V.
• ADC-conversion-complete interrupt signal
Table E. 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic
Pin Description
ADC[0] (Ym, pin 135)
ADC[1] (sXp, pin 134)
ADC[2] (sXm, pin 133)
ADC[3] (sYp, pin 132)
ADC[4] (sYm, pin 131)
External Analog Measurement Input
External Analog Measurement Input
External Analog Measurement Input
External Analog Measurement Input
External Analog Measurement Input
DS653PP3
©Copyright 2005 Cirrus Logic (All Rights Reserved)
7