CS49300_06 Datasheet, PDF (9/90 Pages) Cirrus Logic – Multi-Standard Audio Decoder Family

CS49300 Family DSP
1.6. Switching Characteristics —
RESET
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C_L = 20 pF)
Parameter
Symbol
Min
RESET minimum pulse width low (-CL)
(Note 5)
T_rstl
100
RESET minimum pulse width low (-IL)
(Note 5)
T_rstl
530
All bidirectional pins high-Z after RESET low
(Note 6) T_rst2z
-
Configuration bits setup before RESET high
T_rstsu
50
Configuration bits hold after RESET high
T_rsthld
15
Max
Unit
-
µs
-
µs
100
ns
-
ns
-
ns
Notes: 5. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down
resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down
resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.
6. This specification is characterized but not production tested.
RESET
RD, WR,
PSEL, ABOOT
All Bidirectional
Pins
T_rst2z
T_rstl
T_rstsu T_rsthld
Figure 1. RESET Timing
1.7. Switching Characteristics —
CLKIN
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C_L = 20 pF, PLL Enabled)
Parameter
Symbol
Min
Max
Unit
CLKIN period for internal DSP clock mode
CLKIN high time for internal DSP clock mode
CLKIN low time for internal DSP clock mode
T_clki
35
T_clkih
14
T_clkil
14
3800
ns
-
ns
-
ns
CLKIN
T_clkih
T_clki
T_clkil
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable
DS339F7
9