CS49300_06 Datasheet, PDF (35/90 Pages) Cirrus Logic – Multi-Standard Audio Decoder Family

CS49300 Family DSP
4. POWER
The CS493XX requires a 2.5V digital power supply
for the digital logic within the DSP and a 2.5V
analog power supply for the internal PLL. There
are three digital power pins, VD1, VD2 and VD3,
along with three digital grounds, DGND1, DGND2
and DGND3. There is one analog power pin, VA
and one analog ground, AGND. The DSP will
perform at its best when noise has been eliminated
from the power supply. The recommendations
given below for decoupling and power conditioning
of the CS493XX will help to ensure reliable
performance.
4.1. Decoupling
It is good practice to decouple noise from the
power supply by placing capacitors directly
between the power and ground of the CS493XX.
Each pair of power pins (VD1/DGND, VD2/DGND,
VD3/DGND, VA/AGND) should have its own
decoupling capacitors. The recommended
procedure is to place both a 0.1uF and a 1uF
capacitor as close as physically possible to each
power pin. The 0.1uF capacitor should be closest
to the part (typically 5mm or closer).
4.2. Analog Power Conditioning
In order to obtain the best performance from the
CS493XX’s internal PLL, the analog power supply
(VA) must be as clean as possible. A ferrite bead
should be used to filter the 2.5V power supply for
the analog portion of the CS493XX. This power
scheme is shown in the typical connection
diagrams.
4.3. Ground
For two layer applications, care should be taken to
have sufficient ground between the DSP and parts
in which it will be interfacing (DACs, ADCs, DIR,
microcontrollers, external memory etc). If there is
not sufficient ground, a potential will be seen
between the ground reference of the DSP and the
interface parts and the noise margin will be
significantly reduced potentially causing
communication or data integrity problems.
4.4. Pads
The CS493XX incorporate 3.3V tolerant pads. This
means that while the CS493XX power supplies
require 2.5 volts, 3.3 volt signals can be applied to
the inputs without damaging the part.
5. CLOCKING
The CS493XX clock manager incorporates a
programmable phase locked loop (PLL) clock
synthesizer. The PLL takes an input reference
clock and produces all the internal clocks required
to run the internal DSP and to provide master
mode timing to the audio input/output peripherals.
The clock manager also includes a 33-bit system
time clock (STC) to support audio and video
synchronization.
The PLL can be internally bypassed by connecting
the CLKSEL pin to VD. This connection
multiplexes the CLKIN pin directly to the DSP
clock. Care should be taken to note the minimum
CLKIN requirements when bypassing the PLL.
The PLL reference clock has three possible
sources that are routed through a multiplexer
controlled by the DSP: SCLKN2, SCLKN1, and
CLKIN. Typically, in audio/video environments like
set-top boxes, the CLKIN pin is connected to
27 MHz. In other scenarios such as an A/V
receiver design, the PLL can be clocked through
the CLKIN pin with even multiples of the desired
sampling rate or with an already available clock
source. Typically a 12.288 MHz CLKIN is used in
this scenario so that the same oscillator can be
used for the DSP and ADC.
The clock manager is controlled by the DSP
application software. The software user’s guide for
the application code being used should be
referenced for what CLKIN input frequency is
supported.
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