CS4362_08 Datasheet, PDF (9/42 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4362
SWITCHING CHARACTERISTICS
(For KQZ T_A = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, C_L = 30 pF)
Parameters
Symbol
Min
Typ
MCLK Frequency
(Note 15)
Single-Speed Mode
1.024
-
Double-Speed Mode
6.400
-
Quad-Speed Mode
6.400
-
MCLK Duty Cycle
40
50
Input Sample Rate
Single-Speed Mode Fs
4
-
Double-Speed Mode Fs
50
-
Quad-Speed Mode Fs
100
-
LRCK Duty Cycle
45
50
SCLK Pulse Width Low
SCLK Pulse Width High
t_sclkl
20
-
t_sclkh
20
-
SCLK Period
t_sclkw
--------2---------
MCLK
-
Max
51.2
51.2
51.2
60
50
100
200
55
-
-
-
Units
MHz
MHz
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
LRCK1 to LRCK2 frequency ratio
(Note 16)
(Note 17)
t_sclkw
t_slrd
t_slrs
t_sdlrs
t_sdh
--------4---------
MCLK
20
20
20
20
0.25
-
-
-
-
-
1.00
-
ns
-
ns
-
ns
-
ns
-
ns
4.00
Notes:
15. See Table 5 on page 27 for suggested MCLK frequencies
16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK
t _slrd
t _slrs
t _sclkh
t _sclkl
SCLK
SDATA
t _sdlrs
t _sdh
Figure 1. Serial Mode Input Timing
DS257F2
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