CS4223 Datasheet, PDF (9/32 Pages) Cirrus Logic – 24-Bit 105 dB Audio Codec with Volume Control

CS4223 CS4224
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE (CS4224)
(T_A = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
I²C^® Mode (SPI/I2C = 1)
SCL Clock Frequency
RST rising edge to Start
f_scl
-
(Note 15)
t_irs
50
Bus Free Time between transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low Time
t_low
4.7
Clock High Time
t_high
4.0
Setup time for repeated Start Condition
t_sust
4.7
SDA hold time for SCL falling
(Note 16) t_hdd
0
SDA setup time to SCL rising
t_sud
250
Rise time of SCL
t_rc
-
Fall time of SCL
t_fc
-
Rise time of SDA
t_rd
-
Fall time of SDA
t_fd
-
Setup time for Stop Condition
t_susp
4.7
100
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Notes: 15. Not tested but guaranteed by design.
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t _irs
Stop
Start
SDA
SCL
t _buf
t _hdst
t _high
t _low t _hdd
Repeated
Start _{t rd}
t _hdst
t _fc
t _sud
t _sust
t _rc
Stop
t _fd
t _susp
Figure 3. I²C Control Port Timing
DS290PP3
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