WM8956 Datasheet, PDF (71/80 Pages) Cirrus Logic – Hi-Fi DAC with 1W Stereo Class D Speaker Drivers

Production Data
REGISTER BIT
ADDRESS
2:0
LABEL
ACGAIN[2:0]
R52 (34h) 8:6
PLL (1)
OPCLKDIV[2:0]
5
SDM
4
PLLPRESCALE
3:0 PLLN[3:0]
R53 (35h) 8
PLL (2)
7:0
PLLK[23:16]
R54 (36h) 8
PLL (3)
7:0
PLLK[15:8]
R55 (37h) 8
PLL (4)
7:0
PLLK[7:0]
DEFAULT
DESCRIPTION
000
000
0
0
1000
0
00110001
0
00100110
0
11101001
AC Speaker Boost (Boosts speaker AC output
signal by up to 1.8 x on left and right channels)
000 = 1.00x boost (+0dB)
001 = 1.27x boost (+2.1dB)
010 = 1.40x boost (+2.9dB)
011 = 1.52x boost (+3.6dB)
100 = 1.67x boost (+4.5dB)
101 = 1.8x boost (+5.1dB)
110 to 111 = Reserved
SYSCLK Output to GPIO Clock Division ratio
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 5.5
101 = SYSCLK / 6
Enable Integer Mode
0 = Integer mode
1 = Fractional mode
Divide MCLK by 2 before input to PLL
0 = Divide by 1
1 = Divide by 2
Integer (N) part of PLL input/output frequency
ratio. Use values greater than 5 and less than
13.
Reserved
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Reserved
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Reserved
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
WM8956
REFER TO
Analogue
Outputs
General
Purpose Input /
Output
Clocking and
Sample Rates
Clocking and
Sample Rates
Clocking and
Sample Rates
Clocking and
Sample Rates
Clocking and
Sample Rates
Clocking and
Sample Rates
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PD, November 2011, Rev 4.1
71