WM8956 Datasheet, PDF (27/80 Pages) Cirrus Logic – Hi-Fi DAC with 1W Stereo Class D Speaker Drivers

Production Data
WM8956
REGISTER
ADDRESS
R5 (05h)
DAC Control (1)
BIT
LABEL
3 DACMU
R6 (06h)
DAC Control (2)
3 DACSMM
2 DACMR
Table 10 DAC Soft-Mute Control
DEFAULT
DESCRIPTION
1
Digital Soft Mute
1 = Mute
0 = No mute (signal active)
0
DAC Soft Mute Mode
0 = Disabling soft-mute (DACMU=0)
will cause the volume to change
immediately to the LDACVOL /
RDACVOL settings
1 = Disabling soft-mute (DACMU=0)
will cause the volume to ramp up
gradually to the LDACVOL /
RDACVOL settings
0
DAC Soft Mute Ramp Rate
0 = Fast ramp (fs/2, providing
maximum delay of 10.7ms at fs=48k)
1 = Slow ramp (fs/32, providing
maximum delay of 171ms at fs=48k)
DAC DE-EMPHASIS
Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD
with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of
48kHz, 44.1kHz and 32kHz.
REGISTER
ADDRESS
R5 (05h)
DAC Control (1)
BIT
LABEL
2:1 DEEMPH
[1:0]
Table 11 DAC De-Emphasis Control
DEFAULT
DESCRIPTION
00
De-Emphasis Control
11 = 48kHz sample rate
10 = 44.1kHz sample rate
01 = 32kHz sample rate
00 = No de-emphasis
DAC OUTPUT PHASE AND MONO MIXING
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to
high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low
distortion.
In normal operation, the left and right channel digital audio data is converted to analogue in two
separate DACs. There is a mono-mix mode where the two audio channels are mixed together digitally
and then converted to analogue using only one DAC, while the other DAC is switched off. The mono-
mix signal can be selected to appear on both analogue output channels. The mono mix is
automatically attenuated by 6dB to prevent clipping.
The DAC output defaults to non-inverted. Setting DACPOL[0] bit will invert the left DAC output phase
and setting DACPOL[1] bit will invert the right DAC output phase.
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PD, November 2011, Rev 4.1
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