CS4297 Datasheet, PDF (7/46 Pages) Cirrus Logic – CrystalClear SoundFusion Audio Codec 97

CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
DIGITAL CHARACTERISTICS (AVss = DVss = 0 V (See Grounding and Layout section))
Parameter
Symbol
Min
Typ
Max
Unit
Low level input voltage
V_il
-
-
0.16 x DVdd V
High level input voltage
V_{ih 0.40 x DVdd}
-
-
V
High level output voltage
V_{oh 0.70 x DVdd 0.99 x DVdd}
-
V
Low level output voltage
V_ol
-
0.03 0.10 x DVdd V
Input Leakage Current (AC-link inputs)
-10
-
10
µA
Output Leakage Current (Tri-stated AC-link outputs)
-10
-
10
µA
Output buffer drive current
(Note 4)
-
100
400
µA
SERIAL PORT TIMING
Parameter
Symbol Min
RESET Timing
DVdd 90% maximum value to RESET# inactive pre-delay
(Note 4) ^TVdd2rst#
1.5
RESET# active low pulse width
T_{rst_low}
1.0
RESET# inactive to BIT_CLK start-up delay
T_rst2clk
-
1st SYNC active to CODEC READY set
T_sync2crd
-
Clocks
BIT_CLK frequency
-
BIT_CLK period
T_{clk_period}
-
BIT_CLK output jitter (depends on XTAL_IN source)
-
BIT_CLK high pulse width
T_{clk_high}
-
BIT_CLK low pulse width
T_{clk_low}
-
SYNC frequency
-
SYNC period
T_{sync_period}
-
SYNC high pulse width
T_{sync_high}
-
SYNC low pulse width
T_{sync_low}
-
SYNC active to RESET# inactive pre-delay
T_rst2snyc
-
Data Setup and Hold
Output Propagation delay from rising edge of BIT_CLK
T_prop
-
Output hold from falling edge of BIT_CLK
T_ohold
5
Input setup time from falling edge of BIT_CLK
T_isetup
10
Input hold time from falling edge of BIT_CLK
T_ihold
0
Input Signal rise time
T_irise
2
Input Signal fall time
T_ifall
2
Output Signal rise time
(Note 4) ^Tofall
2
Output Signal fall time
(Note 4) ^Tofall
2
Typ
-
-
42.7
40.6
12.288
81.4
-
40.7
40.7
48
20.8
1.3
19.5
-
6
-
-
-
-
-
4
4
Max Unit
-
ms
-
µs
-
ms
-
µs
-
MHz
-
ns
750
ps
-
ns
-
ns
-
kHz
-
µs
-
µs
-
µs
250
ms
8
ns
-
ns
-
ns
-
ns
6
ns
6
ns
6
ns
6
ns
DS242F5
7