CS4228A Datasheet, PDF (7/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol Min
Typ
RST Low Time
(Note 9)
1
-
SCLK Falling Edge to SDOUT Output Valid
(DSCK=0) t_dpd
-
LRCK Edge to MSB Valid
t_lrpd
-
SDIN Setup Time Before SCLK Rising Edge
t_ds
-
SDIN Hold Time After SCLK Rising Edge
t_dh
-
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
t_mslr
+10
50
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge
LRCK Edge to SCLK Rising
t_sckw
-
t_sckh
50
-
t_sckl
50
-
(DSCK=0) t_lrckd
25
-
(DSCK=0) t_lrcks
25
-
Max
-
50
20
10
30
Units
ms
ns
ns
ns
ns
-
ns
-
%
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 9. After powering up the CS4228A, RST should be held low until the power supplies and clocks are settled.
SCLK*
(output)
LRCK
(output)
SDOUT
t _mslr
Figure 1. Serial Audio Port Master Mode Timing
LRCK
(input)
t _lrckd
t _lrcks
t _sckh
tsckl
SCLK*
(input)
SDIN1
SDIN2
SDIN3
SDOUT
t _sckw
t_{lrpd tds}
tdh
MSB
tdpd
MSB-1
*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.
Figure 2. Serial Audio Port Slave Mode Timing
DS511PP1
7