CS4228A Datasheet, PDF (25/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
5.9 Serial Port Mode
Address 0x0D
7
DCK1
1
6
DCK0
0
5
DMS1
0
4
DMS0
0
3
RESERVED
0
2
DDF2
1
DCK1:0
Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)
1
DDF1
0
DCK1:0
0
1
2
3
BRM (Fs)
32 (1)
48 (2)
*64
128
HRM (Fs)
(3)
(3)
32 (1)
64
Notes: 1. All formats will default to 16 bits
2. External Slave mode only
3. Invalid mode
DMS1:0
DDF2:0
Sets the master/slave mode of the serial audio port
*0 - Slave (External LRCLK, SCLK)
1 - Reserved
2 - Reserved
3 - Master (No 48 Fs SCLK in BRM
Serial Port Data Format
0 - Right Justified, 24-bit
1 - Right Justified, 20-bit
2 - Right Justified, 16-bit
3 - Left Justified, maximum 24-bit
*4 - I²S compatible, maximum 24-bit
5 - One-line Data Mode, available in BRM only
6 - Reserved
7 - Reserved
5.10 Chip Status
Address 0x0E
7
6
5
4
3
2
1
CLKERR
ADCOVL
RESERVED
X
X
0
0
0
0
0
CLKERR
ADCOVL
Clocking system status, read only
0 - No Error
1 - No MCLK is present, or a request for clock change is in progress
ADC overflow bit, read only
0 - No overflow
1 - ADC overflow has occurred
0
DFF0
0
0
0
DS511PP1
25