WM9081 Datasheet, PDF (61/103 Pages) Cirrus Logic – Mono DAC with 2.6W Class AB/D Speaker Driver, Dynamic Range Controller and ReTune™ Mobile Parametric Equalizer

Rev 4.0
WM9081
TOCLK CONTROL
A timeout clock (TOCLK) is derived from CLK_SYS as an input to the zero-cross volume update
function. This clock is enabled by register bit CLK_TO_ENA, and its frequency is controlled by
CLK_TO_RATE, as described in Table 38.
REGISTER
ADDRESS
R12 (0Ch)
Clock
Control1
BIT
LABEL
9:8 CLK_TO_DIV
[1:0]
R14 (0Eh)
2
Clock
Control3
Table 38 TOCLK Control
CLK_TO_ENA
DEFAULT
DESCRIPTION
00
TOCLK (timeout/ slow clock)
frequency select
00 = 125Hz
01 = 250Hz
10 = 500Hz
11 = 1kHz
0
TOCLK (timeout/ slow clock) Enable
0 = Disabled
1 = Enabled
OPCLK CONTROL
A clock output (OPCLK) derived from CLK_SYS may be output on the MCLK pin. This clock is
enabled by register bit CLK_OP_ENA, and its frequency is controlled by CLK_OP_DIV.
This output is only supported when MCLK is not selected as an input to the WM9081.
REGISTER
ADDRESS
R12 (0Ch)
Clock
Control1
BIT
LABEL
12:10 CLK_OP_DIV
[2:0]
R14 (0Eh)
Clock
Control3
5
CLK_OP_ENA
Table 39 OPCLK Control
DEFAULT
DESCRIPTION
000
OPCLK Clock Divider
000 = CLK_SYS
001 = CLK_SYS / 2
010 = CLK_SYS / 3
011 = CLK_SYS / 4
100 = CLK_SYS / 6
101 = CLK_SYS / 8
110 = CLK_SYS / 12
111 = CLK_SYS / 16
0
Clock Output Enable
0 = Disabled
1 = Enabled
This bit enables OPCLK output on
the MCLK pin.
Frequency is set by CLK_OP_DIV.
FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference
sources and frequencies. The FLL can use either MCLK, BCLK or LRCLK as its reference, which may
be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is tolerant
of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The FLL
characteristics are summarised in “Electrical Characteristics”.
Note that the FLL can be used to generate a free-running clock in the absence of an external
reference source. This is described in the “Free-Running FLL Clock” section below.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency F_REF, it is
recommended that the FLL be reset by setting FLL_ENA to 0.
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