WM9081 Datasheet, PDF (27/103 Pages) Cirrus Logic – Mono DAC with 2.6W Class AB/D Speaker Driver, Dynamic Range Controller and ReTune™ Mobile Parametric Equalizer

WM9081
CONTROL WRITE SEQUENCER
The Control Write Sequencer forms part of the WM9081 control interface logic. It provides the ability
to perform a sequence of register write operations with the minimum of demands on the host
processor - the sequence may be initiated by a single operation from the host processor and then left
to execute independently.
Default sequences for controlling the Speaker and Lineout signal paths are provided (see “Default
Sequences” section).
When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The host
processor informs the sequencer of the start index of the required sequence within the sequencer’s
memory. At each step of the sequence, the contents of the selected register fields are read from the
sequencer’s memory and copied into the WM9081 control registers. This continues sequentially
through the sequencer’s memory until an “End of Sequence” bit is encountered; at this point, the
sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the write
sequence is important, the sequencer is programmed with time delays for specific steps within the
sequence.
Note that the Control Write Sequencer’s internal clock is derived from the internal clock CLK_SYS
which must be enabled by setting CLK_SYS_ENA (see “Clocking and Sample Rates”). The clock
division from CLK_SYS is handled transparently by the WM9081 without user intervention, provided
that the CLK_SYS and sample rate control fields are set correctly.
INITIATING A SEQUENCE
The Register fields associated with running the Control Write Sequencer are described in Table 8.
Note that the operation of the Control Write Sequencer also requires the internal clock CLK_SYS to
be enabled via the CLK_SYS_ENA (see “Clocking and Sample Rates”).
The Write Sequencer is enabled by setting the WSEQ_ENA bit. The start index of the required
sequence must be written to the WSEQ_START_INDEX field. Setting the WSEQ_START bit initiates
the sequencer at the given start index.
The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.
The current status of the Write Sequencer can be read using two further register fields - when the
WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the
Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal read/write
operations to the Control Registers cannot be supported. The index of the current step in the Write
Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an indicator of the
sequencer’s progress. On completion of a sequence, this field holds the index of the last step within
the last commanded sequence.
When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_BUSY_EINT flag in
Register R26 (1Ah). (Note that the WSEQ_BUSY_EINT flag is asserted to indicate that the WSEQ is
NOT busy.) This flag can be used to generate an Interrupt Event on completion of the sequence; this
is indicated via the I¯R¯Q¯ pin. See “Interrupts” for details of hardware output of the Write Sequencer
status via the I¯R¯Q¯ pin.
REGISTER
ADDRESS
R38 (26h)
Write
Sequencer 0
BIT
LABEL
15 WSEQ_ENA
9 WSEQ_ABORT
DEFAULT
DESCRIPTION
0
Write Sequencer Enable.
0 = Disabled
1 = Enabled
0
Writing a 1 to this bit aborts the
current sequence and returns control
of the device back to the serial
control interface.
Rev 4.0
27