SA56 Datasheet, PDF (6/7 Pages) Cirrus Logic – PULSE WIDTH MODULATION AMPLIFIER

SA56
OPERATING
CONSIDERATIONS
MODES OF OPERATION
The following chart shows the 3 modes of operation.
Mode
2 Quadrant – Analog Mode
2 Quadrant – Digital Mode
4 Quadrant – Digital Mode
C_PWM
pin 12
Connect ca-
pacitor to set
frequency
SIG_GND
SIG_GND
SIG_GND
PWM
pin 17
Analog control
voltage
(1 – 4V)
Modulation In
Modulation In
High (V_DD)
DIR
pin 16
Low (SIG_GND)
High (V_DD)
Low (SIG_GND)
Modulated In
A_OUT
pins 21, 23
Control voltage
greater than V_REF:
(A_OUT – B_OUT)< 0
average
voltage
High (V_S)
PWM
DIR
B_out
pins 2, 3
Control voltage
greater than V_REF:
(B_OUT – A_OUT)> 0
average
voltage
PWM
High (V_S)
DIR
4-QUADRANT - ANALOG MODE
The SA56 can operate in 4-quadrant mode with analog or
digital inputs. In the analog mode, the capacitor from C_PWM to
SIG_GND sets the frequency of an internal triangular ramp sig-
nal. See Figure 2. An analog voltage applied to the PWM pin
is compared to a 2.5 volt reference within the SA56 thereby
governing the duty cycle of the output. Note that the analog
pin DIR pin 16 is connected to signal ground (SIG_GND).
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OPERATING WITH DIGITAL INPUTS
Two and 4-quadrant operation are possible with the SA56
when driven with a digital PWM signal from a microcontroller or
DSP. When using a digital modulation signal, tie the C_PWM pin
to SIG_GND to disable the internal oscillator and ramp generator.
When operating in the digital mode, pulse widths should be no
less than 100 ns and the switching frequency should remain
less than 500 kHz. This will allow enough time for the output
MOSFETs to reach their full on and off states before receiving
a command to reverse state.
2-QUADRANT - DIGITAL MODE
Two-quadrant operation of the FETs is realized by driving
PWM pin 17 of the SA56 with a digital PWM signal supplied
by a microcontroller or DSP, as depicted in Figure 3. When
using a digital modulation signal, connect the C_PWM pin to
SIG_GND to disable the internal oscillator and its companion
ramp generator.
A digital PWM signal applied to the PWM pin controls the
output duty cycle at one output pin while the other output pin is
held "HIGH". The input at the DIR pin (V_DD or SIG_GND) governs
the output behavior. If DIR is a logic HIGH, the A_OUT output
will be held high and the B_OUT output will be switched as the
complement of the PWM input signal. The average output at
A_OUT will always be greater than at B_OUT. Whereas if DIR is a
logic LOW, the B_OUT output will be held "HIGH" and the A_OUT
output will be switched.
Operating in two-quadrant mode reduces switching noise
and power dissipation, but limits the ability to control the motor
at very low speed.
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