SA56 Datasheet, PDF (5/7 Pages) Cirrus Logic – PULSE WIDTH MODULATION AMPLIFIER

OPERATING
CONSIDERATIONS
SA56
GENERAL
Please read "SA56 Design Ideas" that covers the various
SA56 applications in considerable detail. Also see Application
Note 1 "General Operating Considerations" which covers stabil-
ity, power supplies, heat sinking, mounting, and specification
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit, heat sink selection,
Apex's complete Application Notes library, Technical Seminar
Workbook and Evaluation Kits.
GROUND PINS
The two SIG_GND pins, 9 & 10, are for input signal grounds.
Pins 1 and 23, P_GND, are power grounds. The P_GND & SIG_GND
pins are connected at one point inside the IC. It is also recom-
mended the user connect both pins at a single point on the board
in a way that no current flows through that connection.
POWER SUPPLY BYPASSING
Bypass capacitors to power supply terminals V_S and V_DD must
be connected physically close to the pins to prevent erratic,
low-efficiency operation and excessive ringing at the outputs.
Electrolytic capacitors, at least 10 μF per output ampere are
required for suppressing V_S to P_GND noise. High quality ceramic
capacitors (X7R) 1 μF or greater should also be used. Only ca-
pacitors rated for switching applications should be considered.
The bypass capacitors must be located as close to the power
supply pins as possible. Due to the very fast switching times
of the outputs, the inductance of 1 inch of circuit trace could
cause noticeable degradation in performance. The bypassing
requirements of V_DD are less stringent, but still necessary. A
0.1 μF to 0.47 μF capacitor connected directly between the
V_DD and SIG_GND pins will suffice.
PIN DESCRIPTIONS
Pin # Name
1,23 P_GND
2,3 B_out
4,5, V_S
19,20
6 SC
7
T_LIM
Description
Power high current ground return path of the
motor.
Half bridge output B
High voltage supply
The short-circuit protection circuits will sense
a direct short from either output (A_OUT or
B_OUT) to P_GND or V_S – as well as across the
load. If the high-current protection circuit
engages it will place all four MOSFETs in the
tristate state (high-impedance output). The
SC output, pin 6, will go HIGH though not
latch, thereby denoting that this protection
feature has been triggered.
Temperature limit, CMOS. This pin can be
used as a flag for an over-temperature con-
dition. Under normal operation this pin will
be logic low. When a junction temperature
exceeds approximately 160°C this pin will
change to logic high and the output will be
latched off. Grounding this pin disables over
temperature protection. This pin should be
left open if over temperature protection is
desired but the flag is not used.
8
I_SEN
Current Sense output and programmable
current limit. A current proportional to the
output current is sourced by this pin. Typi-
cally this pin is connected to a resistor for
programmable current limit or transconduc-
tance operation.
9,10 SIG_GND Ground connection for all internal digital and
low-current analog circuitry.
11 FAULT This pin latches high whenever the four
MOSFETs have been placed in the tristate
condition which occurs when either the
high-current or the thermal protection has
engaged.
12 C_PWM
An external timing capacitor is connected to
this pin to set the frequency of the internal
oscillator and ramp generator for analog
control mode. The capacitor value (pF)
= 4.05x10⁷/F_SW, where F_SW = the desired
switching frequency. This pin is grounded
for digital control mode.
13,14 V_DD
5V supply for input logic and low voltage
analog circuitry.
15 V_REF
Reference voltage. Can be used at low cur-
rent for biasing analog loop circuits.
16 DIR
Direction of rotation control; In 2 quadrant,
digital control, determines the active output
FETs. This pin should be grounded in analog
control mode.
17 PWM CMOS/TTL input for digital PWM control, or
1-4V analog input for duty cycle control in
analog control mode.
18 DISABLE Following a fault, pulling the DISABLE pin
HIGH and then LOW will reset a latched
fault condition. (When pulled HIGH, all four
output MOSFETs are disabled. A logic LOW
on this pin allows the four output FETs to
function normally.) When the DISABLE and
FAULT pins are tied to a microcontroller, the
FAULT pin will generate an interrupt in the
microcontroller, so that the interrupt, can in
turn, generate a pulse on the DISABLE pin.
When a fault occurs, the SA56 fault circuitry
will be reset.
21,22 A_OUT
Half bridge output A
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