CDB5460A Datasheet, PDF (6/28 Pages) Cirrus Logic – Evaluation Board and Software

CDB5460A
1.2.2 Digital Section
The schematics for the digital section are shown in
Figure 10 and Figure 11. The digital section con-
tains the microcontroller, test switches, a Maxim
MAX3232 interface chip, and 32K bytes of
SRAM, and one serial EEPROM. The test switches
aid in debugging communication problems be-
tween the CDB5460A and the PC. The microcon-
troller derives its clock from a 20.0 MHz crystal.
From this, The RS-232 data conversion IC (10) is
configured to communicate via RS-232 at 9600
baud, no parity, 8-bit data, and 1 stop bit.
1.2.3 Power Supply Section
Figure 12 illustrates the power supply connections
to the evaluation board. The VA+ post supplies the
positive analog section of the evaluation board, the
LT1019 and the ADC. The VA- post supplies the
negative analog voltage circuitry. Note, this termi-
nal is grounded when powering the CDB5460A
from a single +5 Volt analog supply. The VD+ post
supplies the digital section of the ADC and level
shifter. The Vu+ post supplies the digital section of
the evaluation board, the 80C51, the reset circuitry,
and the RS-232 interface circuitry. Note, the
board’s digital section supplied via Vu+ post, must
be +5 Volts only. Table 2 shows the various power
connections with the required jumper settings on
J12 and J11.
1.3 Using the Evaluation Board
The CS5460A is a highly integrated device, con-
taining dual ADCs with a computational unit. The
CS5460A and CDB5460A data sheets should be
read thoroughly and understood before using the
CDB5460A evaluation board. The CS5460A con-
tains a programmable gain amplifier (PGA), two
∆Σ modulators, two high rate filters, an on-chip ref-
erence, and power calculation engine to compute
Energy, V_RMS, I_RMS, and Instantaneous Power.
The PGA sets the input levels of the current chan-
nel at either 30 mV_RMS or 150 mV_RMS (for VRE-
FIN = 2.5 V). The on-chip reference can provide
the necessary 2.5 V reference. This output (VRE-
FOUT) is used to supply the VREFIN pin with
2.5 V. The ∆Σ modulators and high rate digital fil-
ter allow the user to measure instantaneous voltage,
current, and power at a output word rate of 4000 Hz
when a 4.096 MHz clock source is used. Table 3
describes the various headers, jumpers and DIP
switches on the CDB5460A evaluation board. DIP
switch S1 is used to control the 80C51. Table 4 il-
lustrates the varies setting of the DIP Switch S1.
Power Supplies
Analog Digital
+5V
+5V
+5V
+3V
±2.5V
+3V
Power Post Connections
VA+ VA- GND VD+
Vu+
+5 NC GND
+5
NC
Jumpers
J12
J11
Vu+ O
VD+ O
VD+ O
VA+ O
O VDDD
O VDDD
O D+
O D+
VA- _{O O GND}
A- O O GND
+5 NC GND
+3
Vu+ O O VDDD
+5
VD+ O O VDDD
VA- _{O O GND}
VD+ O O D+
A- O O GND
VA+ O O D+
+2.5
-2.5 GND
+3
Vu+ O O VDDD
+5
VD+ O O VDDD
VD+ O O D+
VA+ O O D+
Table 2. Power Supply Connections
VA- O O GND
A- O O GND
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