CDB5460A Datasheet, PDF (28/28 Pages) Cirrus Logic – Evaluation Board and Software

CDB5460A
3. ADDENDUM
3.1 Board Modifications for Charge Pump
The CDB5460A can be modified by the user, to in-
clude a charge pump circuit, whose output could be
used to supply the VA- supply pin in the +2.5V and
-2.5V analog power configuration. The diagram
below illustrates the schematic of such a circuit.
The components must be added by the user.
1) Header H1 allows a clock source to be clipped
across J1 with J2 open to analyze the charge
pump by itself or drive it asynchronous to the
CS5460A. With J1 open and J2 closed, the
pump is clocked synchronously with the
CS5460A. For best results, the charge pump
should be clocked synchronously with the
CS5460A.
2) The charge pump is constructed from compo-
nents C1, C2, D1 and D2. D1 and D2 are
BAT85 schottky diodes chosen for their speed
and low forward voltage. Capacitor C1 pro-
vides the necessary current at 4.096 MHz. Ca-
pacitor C2 provides extra storage if the load on
A- is increased. If the external reference is re-
moved (and therefore the CS5460A is the only
load on A-) C2 can be removed. The bypass ca-
pacitors from VA+ to A- will be sufficient.
3) Header H2 connects the charge pump to A-. H2
can be removed to analyze the unloaded perfor-
mance of the charge pump. This should be
closed for "charge-pump" mode operation.
4) A four-pin socket (U1) is added to connect an
optional clock oscillator to the XIN pin and eas-
ily operate the CS5460A in "external clock"
mode.
H1
HDR
J1
AGND
C1
1.0 nF
J2
D2
BAT 85
H2
HDR
A-
D1
BAT 85
C2
1.0 nF
AGND
AGND
XIN
CS5460
DGND
XINT
HDR 10
MC
DGND
D+
CLOCK
Already Exists
Figure 16. CDB5460A Modifications for A- Charge Pump
28