CS8952T Datasheet, PDF (59/86 Pages) Cirrus Logic – 100BASE E-X AND 10BASE-T TRANSCEIVER

CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Self Status Register - Address 19h (Cont.)
BIT
5
4:0
NAME
CIM Status
PHY Address Field
TYPE
Read Only
Read/Write
RESET
0
Reset to the val-
ues on the
PHYAD[4:0] pins.
DESCRIPTION
When clear, this bit indicates that a stable link con-
nection has been detected. When an unstable link is
detected and the Carrier Integrity Monitor Disable bit
in the PCS Sub-Layer Configuration Register
(address 17h) is clear, this bit is set and latched. It will
remain set until this register is read.
The value on pins PHYAD[4:0] are latched into this
field at power-up or reset. These bits define the PHY
address used by the management layer to address
the PHY. The external logic must know this address
in order to select this particular CS8952T’s registers
individually via the MDIO and MDC pins.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
59