CS4202_05 Datasheet, PDF (54/66 Pages) Cirrus Logic – Audio Codec ’97 with Headphone Amplifier

CS4202
11. GROUNDING AND LAYOUT
Figure 26 on page 55 shows the conceptual layout
for the CS4202 in XTAL or OSC clocking modes.
The decoupling capacitors should be located phys-
ically as close to the pins as possible. Also, note the
connection of the REFFLT decoupling capacitors
to the ground return trace connected directly to the
ground return pin, AVss1.
It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4202 ground potential and de-
grading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4202 and any other external analog cir-
cuitry. All analog components and traces should be
located over the analog ground plane and all digital
components and traces should be located over the
digital ground plane.
The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4202. The AC-link digital interface connec-
tion traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC ’97 controller to
the CS4202.
Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.
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