CS4202_05 Datasheet, PDF (43/66 Pages) Cirrus Logic – Audio Codec ’97 with Headphone Amplifier

CS4202
5.3 Serial Data Formats
In order to support a wide variety of serial audio
DACs, the CS4202 can transmit serial data in four
different formats. The desired format is selected
through the SDF[1:0] bits in the Serial Port Control
Register (Index 6Ah). All serial ports use the same
serial data format when enabled. In all cases, LR-
CLK will be synchronous with Fs, and SCLK will
be 64 Fs (BIT_CLK/4). Serial data is transitioned by
the CS4202 on the falling edge of SCLK and latched
by the DACs on the next rising edge. Serial data is
shifted out MSB first in all supported formats, but
LRCLK polarity as well as data justification, align-
ment, and resolution vary. Table 14 shows the prin-
cipal characteristics of each serial format.
SDF[1:0]
LRCLK
Polarity
Data
Justification
Data Alignment
(MSB vs. LRCLK)
Data
Resolution
Timing
Diagram
Recommended
DAC
0 0 negative left justified 1 SCLK delayed
01
positive left justified
not delayed
10
positive right justified
not delayed
11
positive right justified
not delayed
20-bit
20-bit
20-bit
16-bit
Figure 11
Figure 12
Figure 13
Figure 14
CS4334
CS4335
CS4337
CS4338
Table 14. Serial Data Formats and Compatible DACs for the CS4202
LRCK
Left Channel
Right Channel
SCLK
SDATA
LRCK
SCLK
MSB-1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB-1 -2 -3 -4
Figure 11. Serial Data Format 0 (I²S)
+5 +4 +3 +2 +1 LSB
Left Channel
Right Channel
SDATA
LRCK
SCLK
MSB-1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB-1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Figure 12. Serial Data Format 1 (Left Justified)
Left Channel
Right Channel
SDATA 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 13. Serial Data Format 2 (Right Justified, 20-bit data)
LRCK
SCLK
Left Channel
Right Channel
SDATA
DS549PP2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 14. Serial Data Format 3 (Right Justified, 16-bit data)
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