WM8233 Datasheet, PDF (53/146 Pages) Wolfson Microelectronics plc – 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output

WM8233
CLAMP CONFIGURATION
Clamp configuration is the setting for clamp modes and clamp timing configuration in line clamp mode.
See “Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for details of
configuring this register.
TG enabled: This must be enabled when AGC function is used.
Line clamp configuration: Line clamp operation is enabled during CLAMP_RISE ~ CLAMP_FALL
period. Also, the source follower should be set to prevent clamp voltage drop in line clamp mode.
Pixel clamp (Bit clamp) mode: The pixel clamping is enabled during RSMP = high period. This mode
can be used in CDS operation only.
Clamp configuration
Clamp mode
selection
0x04[1]
CLPMD=0
Line clamp
0x04[1]
CLPMD=1
Bit clamp
TG enabled (*1)
Pixel clamp mode (*3)
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
Slave mode
0xA0[1] TGMD=0
TG
enabled
0xA0[0] TG_EN
Line clamp configuration
Clamp timing
configuration
0xB9,0xBA CLAMP_RISE
0xBB,0xBC CLAMP_FALL
Source follower
configuration (*2)
0x05[1] SF_INP
0x05[0] SF_VRLC
Figure 39 Clamp Configuration
Notes:
1. This must be set when Line clamp is used.
2. SF_INP and SF_VRLC must be set both when source follower enabled
3. Pixel clamp can be used in CDS operation only.
Rev 4.7
53