WM8233 Datasheet, PDF (36/146 Pages) Wolfson Microelectronics plc – 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output

WM8233
TG PULSE
The WM8233 can generate 8 TG pulses internally (PO0 – PO7). These pulses are generated by the
toggle point setting registers (TP*) and polarity setting registers (POL*_PO*). WM8233 provided up to
32 toggle point by using TP0 to TP31. PO0-PO7 signals can be assigned to CLK2-CLK11 by
SEL_PCK* and SEL_CLK* register.
TRIGGER DATA
The WM8233 can implement trigger data in LVDS output.(S0,S1,S2,S3 and S4) This can be selected
by two methods. One is the FLAGPIX register which can be set one pixel for each line. The other is to
apply a PO* pulse. Figure 21 shows the trigger data implementation timing.
CHANNEL ID
Also WM8233 can implement channel identification data instead of trigger data. Table 11 shows the
matrix of input channel and channel ID.
ID[2]
ID[1]
ID[0]
IN1
0
0
1
IN2
0
1
0
IN3
0
1
1
IN4
1
0
0
IN5
1
0
1
IN6
1
1
0
Table 11 Channel ID
Channel ID can be assigned to flag data (S0, S1, S2, S3 or S4). The following is the example of
channel ID assignment.
Example: Assigned channel ID to flag data as ID[2] =S1, ID[1]=S2, ID[0]=S3.
If output data is as follows, channel ID will be IN1. (i.e. ID[2] =S1=0, ID[1]=S2=0, ID[0]=S3=1)
A
D5
D4
D3
D2
D1
DCLK
S0
IN1[4]
S4
IN2[6]
IN3[3]
H
S1
IN1[5]
IN2[0]
IN2[7]
IN3[4]
H
S2
IN1[6]
IN2[1]
IN2[8]
IN3[5]
L
IN1[0]
IN1[7]
IN2[2]
IN2[9]
IN3[6]
L
IN1[1]
IN1[8]
IN2[3]
IN3[0]
IN3[7]
L
IN1[2]
IN2[4]
IN3[1]
IN3[8]
H
IN1[3]
S3
IN2[5]
IN3[2]
IN3[9]
H
36
Rev 4.7