CS42418 Datasheet, PDF (5/67 Pages) Cirrus Logic – 110 dB, 192kHz 8-Ch CODEC WITH PLL

CS42418
Figure 52. Quad Speed (slow) Stopband Rejection...................................................................... 60
Figure 53. Quad Speed (slow) Transition Band ............................................................................ 60
Figure 54. Quad Speed (slow) Transition Band (detail) ................................................................ 60
Figure 55. Quad Speed (slow) Passband Ripple .......................................................................... 60
Figure 56. Serial Audio Port Master Mode Timing ........................................................................ 61
Figure 57. Serial Audio Port Slave Mode Timing .......................................................................... 61
Figure 58. Control Port Timing - I2C Format................................................................................. 62
Figure 59. Control Port Timing - SPI Format................................................................................. 63
LIST OF TABLES
Table 1. PLL External Component Values .................................................................................... 15
Table 2. Common OMCK Clock Frequencies .............................................................................. 15
Table 3. Common PLL Output Clock Frequencies....................................................................... 16
Table 4. Slave Mode Clock Ratios ............................................................................................... 16
Table 5. Serial Audio Port Channel Allocations ............................................................................ 17
Table 6. DAC De-Emphasis .......................................................................................................... 34
Table 7. Digital Interface Formats ................................................................................................. 35
Table 8. ADC One_Line Mode ...................................................................................................... 35
Table 9. DAC One_Line Mode ...................................................................................................... 35
Table 10. RMCK Divider Settings ................................................................................................. 37
Table 11. OMCK Frequency Settings ........................................................................................... 38
Table 12. Master Clock Source Select.......................................................................................... 38
Table 13. PLL Clock Frequency Detection.................................................................................... 39
Table 14. Example Digital Volume Settings .................................................................................. 42
Table 15. ATAPI Decode .............................................................................................................. 44
Table 16. Example ADC Input Gain Settings ................................................................................ 45
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