CS42418 Datasheet, PDF (39/67 Pages) Cirrus Logic – 110 dB, 192kHz 8-Ch CODEC WITH PLL

CS42418
5.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only)
7
RATIO7(2¹)
6
RATIO6(2⁰)
5
RATIO5(2^-1)
4
RATIO4(2^-2)
3
RATIO3(2^-3)
2
RATIO2(2^-4)
1
RATIO1(2^-5)
0
RATIO0(2^-6)
5.8.1 OMCK/PLL_CLK RATIO (RATIOX)
Default = sixth
Function:
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
5.9 Clock Status (address 08h) (Read Only)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Active_CLK
2
PLL_CLK2
1
PLL_CLK1
0
PLL_CLK0
5.9.1 SYSTEM CLOCK SELECTION (ACTIVE_CLK)
Default = x
0 - Output of PLL
1 - OMCK
Function:
This bit identifies the source of the internal system clock (MCLK).
5.9.2 PLL CLOCK FREQUENCY (PLL_CLKX)
Default = xxxh
Function:
The CS42418 will auto-detect the ratio between the OMCK and the recovered clock from the PLL,
which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can
be determined, and this information is displayed according to the following table. If the absolute fre-
quency of the PLL clock does not match one of the given frequencies, this register will display the
closest available value.
NOTE: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
PLL_CLK2
0
0
0
0
1
1
1
1
PLL_CLK1
0
0
1
1
0
0
1
1
PLL_CLK0
0
1
0
1
0
1
0
1
Description
8.1920 MHz
11.2896 MHz
12.288 MHz
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
Table 13. PLL Clock Frequency Detection
39