CS4365_08 Datasheet, PDF (44/52 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

6.12 PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
CS4365
0
Reserved
0
6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
44
DS670F2