CS5371_05 Datasheet, PDF (4/22 Pages) Cirrus Logic – Low-power, High-performance ΔΣ Modulators

CS5371 CS5372
ANALOG CHARACTERISTICS (Continued)
Parameter
Specified Temperature Range
Input Characteristics
Input Signal Frequencies
Input Voltage Range
Input Over-range Voltage Tolerance
Input Signal plus Common Mode
(Note 7)
(Note 8)
(Note 8)
Symbol
T_A
BW
VIN
I_OVR
Common Mode Rejection Ratio
Channel Crosstalk (CS5372 only)
Voltage Reference Input
VREF
(VREF+) - (VREF-)
VREF Current
Power Supplies
DC Power Supply Currents
LPWR = 0; MCLK = 2.048 MHz
LPWR = 1; MCLK = 1.024 MHz
(Note 9 and 10)
Analog
Digital
Analog
Digital
Power Down Modes
CS5371
PWDN = 1
PWDN = 1, MCLK = 0
CMRR
CXT
VA
VD
VA
VD
P_D
Min
-40
DC
-
5
(VA-)
+ 0.7V
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
90
-120
2.5
-
5.0
0.2
3.0
0.2
1
10
Max Unit
+85
C
1720
5
-
(VA+)
- 1.7V
-
-
Hz
V_p-p
%F.S.
V
dB
dB
-
V
120
µA
7.0
mA
0.3
mA
4.5
mA
0.3
mA
-
mW
-
µW
CS5372
PWDN1 or PWDN2 = 1
PWDN1 = PWDN2 = 1
PWDN1 = PWDN2 = 1, MCLK = 0
-
25
-
mW
-
1
-
mW
-
10
-
µW
Power Supply Rejection
(Note 11) PSRR
-
90
-
dB
Notes: 7. The upper bandwidth limit is determined by the digital filter. A simple single pole anti-alias filter with a -
3 dB frequency at (MCLK / 256) should be placed in front of each channel.
8. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,
and applies to signal frequencies from DC to the stop-band frequency selected in the digital filter.
9. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.
10. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
oversampled signal bandwidth by a factor of 2.
11. Tested with a 50 Hz 100 mVpp sine wave applied separately to each supply.
4
DS255F3