CDB4391A Datasheet, PDF (4/24 Pages) Cirrus Logic – Evaluation Board for CS4391A

CDB4391A
1. CDB4391A SYSTEM OVERVIEW
The CDB4391A evaluation board is an excellent means of quickly evaluating the CS4391A. The CS8414
digital audio interface receiver provides an easy interface to digital audio signal sources including the ma-
jority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data
through a 10-pin header for system development.
The CDB4391A schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each
partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system dia-
gram also includes the interconnections between the partitioned schematics.
2. CS4391A DIGITAL TO ANALOG CONVERTER
A description of the CS4391A is included in the CS4391A data sheet.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver,
Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-
emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital
audio interface are included in the CS8414 data sheet.
During normal operation, the CS8414 operates in the Channel Status mode where the LED's display chan-
nel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to de-
code the de-emphasis bit from the digital audio interface for control of the CS4391A de-emphasis filter,
when the CS4391A is in stand-alone mode.
When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency informa-
tion mode. The information displayed by the LED's can be decoded by consulting the CS8414 data sheet.
It is likely that the de-emphasis control for the CS4391A will be erroneous and produce an incorrect audio
output if the Error Information Switch is activated and the CS4391A is in the stand-alone mode with in-
ternal serial clock mode selected.
Encoded sample frequency information can be displayed provided a proper clock is being applied to the
FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the
CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of
CSLR/FCK should be selected if the FCK pin is being driven by a clock signal.
The evaluation board has been designed such that the input can be either optical or coax, see Figure 6.
However, both inputs cannot be driven simultaneously.
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DS600DB1