CS42428_05 Datasheet, PDF (39/73 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with PLL

CS42428
5. REGISTER QUICK REFERENCE
Addr Function
7
01h ^ID
page 42
default
02h ^{Power Con-}
trol
page 43
default
Chip_ID3
1
Reserved
0
03h ^Functional
Mode
DAC_FM1
page 43
default
04h ^Interface
Formats
page 45
default
0
DIF1
0
05h _{Misc Control}
page 46
default
Ext ADC
SCLK
0
06h Clock Con- RMCK_DIV1
trol
page 48
default
07h ^OMCK/PLL_
CLK Ratio
page 49
default
0
RATIO7
X
08h Clock Status
page 50
default
Reserved
X
09h- _Reserved
0Ch
Reserved
default
0Dh ^Volume
Control
page 51
default
0Eh ^Channel
Mute
page 52
default
0Fh ^{Vol. Control}
A1
page 53
default
10h ^{Vol. Control}
B1
page 53
default
11h ^{Vol. Control}
A2
page 53
default
12h ^{Vol. Control}
B2
page 53
default
X
Reserved
0
B4_MUTE
0
A1_VOL7
0
B1_VOL7
0
A2_VOL7
0
B2_VOL7
0
6
Chip_ID2
1
PDN_PLL
0
DAC_FM0
0
DIF0
1
HiZ_RMCK
0
RMCK_DIV0
0
RATIO6
X
Reserved
X
Reserved
X
SNGVOL
0
A4_MUTE
0
A1_VOL6
0
B1_VOL6
0
A2_VOL6
0
B2_VOL6
0
5
Chip_ID1
1
PDN_ADC
0
ADC_FM1
0
ADC_OL1
0
Reserved
0
OMCK
Freq1
0
RATIO5
X
Reserved
X
Reserved
X
SZC1
0
B3_MUTE
0
A1_VOL5
0
B1_VOL5
0
A2_VOL5
0
B2_VOL5
0
4
Chip_ID0
1
3
Rev_ID3
X
2
Rev_ID2
X
1
Rev_ID1
X
0
Rev_ID0
X
PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1
PDN
0
0
0
0
1
ADC_FM0
0
Reserved
0
ADC_CLK
SEL
0
DAC_DEM
0
Reserved
0
ADC_OL0 DAC_OL1 DAC_OL0 Reserved CODEC_RJ16
0
0
0
0
0
FREEZE
0
FILTSEL
0
HPF_
FREEZE
0
DAC_SP
M/S
0
ADC_SP
M/S
0
OMCK
Freq0
0
PLL_LRCK SW_CTRL1 SW_CTRL0 FRC_PLL_LK
0
0
0
0
RATIO4
RATIO3
RATIO2
RATIO1
RATIO0
X
X
X
X
X
Reserved Active_CLK PLL_CLK2 PLL_CLK1
X
X
X
X
PLL_CLK0
X
Reserved Reserved Reserved Reserved
Reserved
X
SZC0
X
AMUTE
X
Reserved
X
RAMP_UP
0
1
0
0
A3_MUTE B2_MUTE A2_MUTE B1_MUTE
0
0
0
0
A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1
0
0
0
0
B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1
0
0
0
0
A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1
0
0
0
0
B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1
0
0
0
0
X
RAMP_DN
0
A1_MUTE
0
A1_VOL0
0
B1_VOL0
0
A2_VOL0
0
B2_VOL0
0
DS605F1
39