CS4272 Datasheet, PDF (38/53 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4272
8. REGISTER DESCRIPTION
** All registers are read/write in I²C mode and write only in SPI mode, unless otherwise noted**
8.1 Mode Control 1 - Address 01h
7
6
5
4
3
2
1
M1
M0
Ratio1
Ratio0
M/S
DAC_DIF2 DAC_DIF1
8.1.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample rates.
Table 11. Functional Mode Selection
M1
M0
Mode
0
0
Single-Speed Mode: 4 to 50 kHz sample rates (default)
0
1
Single-Speed Mode: 4 to 50 kHz sample rates
1
0
Double-Speed Mode: 50 to 100 kHz sample rates
1
1
Quad-Speed Mode: 100 to 200 kHz sample rates
0
DAC_DIF0
8.1.2 Ratio Select (Bits 5:4)
Function:
These bits are used to select the clocking ratios in Control Port Mode. Please refer to Table 8, “Clock
Ratios - Control Port Mode With External Crystal,” on page 28 or Table 9, “Clock Ratios - Control Port
Mode Without External Crystal,” on page 29 for information on which of these bits to set to obtain spe-
cific clock ratios.
8.1.3 Master / Slave Mode (Bit 3)
Function:
This bit selects either master or slave operation. Setting this bit will select master mode, while clearing
this bit will select slave mode.
8.1.4 DAC Digital Interface Format (Bits 2:0)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital
Interface Format and the options are detailed in Table 12 and Figures 3-5.
Table 12. DAC Digital Interface Formats
DAC_DIF2 DAC_DIF1 DAC_DIF0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Description
Left Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Right Justified, 20-bit Data
Right Justified, 18-bit Data
Reserved
Reserved
Format
0
1
2
3
4
5
Figure
3
4
5
5
5
5
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DS593F1