CS4272 Datasheet, PDF (36/53 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4272
6.2 I²C Mode
In I²C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock
to data relationship as shown in Figure 18. There is no CS pin. Pin AD0 forms the partial chip address and should be
tied to VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the
CS4272, the LSB of the chip address field, which is the first byte sent to the CS4272, should match the setting of the
AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write,
the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then
followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will
be output after the chip address.
The CS4272 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP
will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, al-
lowing block reads or writes of successive registers.
SDA
001000
ADDR
AD0
R/W ACK
Note 1
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 18. Control Port Timing, I²C Mode
Table 10. Memory Address Pointer (MAP)
7
6
5
INCR
Reserved
Reserved
0
0
0
INCR - Auto MAP Increment Enable
Default = ‘0’.
0 - Disabled
1 - Enabled
MAP(3:0) - Memory Address Pointer
Default = ‘0000’.
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
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