CS42436_07 Datasheet, PDF (38/61 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 6-Out TDM CODEC

CS42436
5.8.2 Software Mode
1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will initially be in a low power state with VQ low. All features will default as
described in the “Register Quick Reference” on page 39.
3. Perform a write operation to the Power Control register (“Power Control (Address 02h)” on page 42) to
set bit 0 to a ‘1’b. This will place the device in a power down state.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Mute all DACs. Muting the DACs suppresses any noise associated with the CODEC's first initialization
after power is applied.
6. Set the PDN bit in the power control register to ‘0’b.Following approximately 2000 LRCK cycles, the de-
vice is initialized and ready for normal operation.
7. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and then unmute the DACs.
8. Normal operation begins.
5.9 Reset and Power-Up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended op-
erating condition to prevent power-glitch-related issues.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 400 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
5.10 Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42436 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figures 1 and 2 show the recommended
power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be
run from the system logic supply.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42436 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42436 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and
VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from
FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and power supply
arrangements.
For optimal heat dissipation from the package, it is recommended that the area directly under the part be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back-
side ground is also recommended.
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