CS42436_07 Datasheet, PDF (24/61 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 6-Out TDM CODEC

CS42436
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C_L = 30 pF)
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
RST Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
f_sck
0
t_srs
20
t_css
20
t_csh
1.0
t_scl
66
t_sch
66
t_dsu
40
(Note 23)
t_dh
15
t_pd
-
t_r1
-
t_f1
-
(Note 24)
t_r2
-
(Note 24)
t_f2
-
6.0
MHz
-
ns
-
ns
-
μs
-
ns
-
ns
-
ns
-
ns
50
ns
25
ns
25
ns
100
ns
100
ns
Notes:
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For f_sck <1 MHz.
RST
t_srs
CS
t_css
t_sch
t_scl
t_csh
t_r2
CCLK
t_f2
t_dsu t_dh
CDIN
CDOUT
MSB
t_pd
MSB
Figure 8. Control Port Timing - SPI Format
24
DS647F2