CS42526_05 Datasheet, PDF (3/93 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
6. REGISTER DESCRIPTION .................................................................................................................. 46
6.1 Memory Address Pointer (MAP) ..................................................................................................... 46
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 46
6.3 Power Control (address 02h) .......................................................................................................... 47
6.4 Functional Mode (address 03h) ...................................................................................................... 48
6.5 Interface Formats (address 04h) .................................................................................................... 50
6.6 Misc Control (address 05h) ............................................................................................................ 51
6.7 Clock Control (address 06h) ........................................................................................................... 53
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 54
6.9 RVCR Status (address 08h) (Read Only) ....................................................................................... 54
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only) ........................................ 56
6.11 Volume Transition Control (address 0Dh) .................................................................................... 57
6.12 Channel Mute (address 0Eh) ........................................................................................................ 59
6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 59
6.14 Channel Invert (address 17h) ....................................................................................................... 59
6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) ............................................................. 60
6.16 ADC Left Channel Gain (address 1Ch) ........................................................................................ 62
6.17 ADC Right Channel Gain (address 1Dh) ...................................................................................... 62
6.18 Receiver Mode Control (address 1Eh) ......................................................................................... 62
6.19 Receiver Mode Control 2 (address 1Fh) ...................................................................................... 64
6.20 Interrupt Status (address 20h) (Read Only) ................................................................................. 64
6.21 Interrupt Mask (address 21h) ....................................................................................................... 65
6.22 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h) ............................................................................................... 66
6.23 Channel Status Data Buffer Control (address 24h) ...................................................................... 66
6.24 Receiver Channel Status (address 25h) (Read Only) .................................................................. 67
6.25 Receiver Errors (address 26h) (Read Only) ................................................................................. 68
6.26 Receiver Errors Mask (address 27h) ............................................................................................ 69
6.27 Mutec Pin Control (address 28h) .................................................................................................. 70
6.28 RXP/General-Purpose Pin Control (addresses 29h to 2Fh) ......................................................... 70
6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) ....................................... 72
6.30 C-Bit or U-Bit Data Buffer (addresses 3Ah to 51h) (Read Only) .................................................. 72
7. PARAMETER DEFINITIONS ................................................................................................................ 73
8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 74
8.1 ADC Input Filter .............................................................................................................................. 74
8.2 DAC Output Filter ........................................................................................................................... 74
9. APPENDIX B: S/PDIF RECEIVER ....................................................................................................... 75
9.1 Error Reporting and Hold Function ................................................................................................. 75
9.2 Channel Status Data Handling ....................................................................................................... 75
9.2.1 Channel Status Data E Buffer Access ................................................................................... 76
9.2.1.1 One-Byte Mode .......................................................................................................... 76
9.2.1.2 Two-Byte Mode .......................................................................................................... 76
9.2.2 Serial Copy Management System (SCMS) ........................................................................... 77
9.3 User (U) Data E Buffer Access ....................................................................................................... 77
9.3.1 Non-Audio Auto-Detection ..................................................................................................... 77
9.3.1.1 Format Detection ....................................................................................................... 77
10. APPENDIX C: PLL FILTER ................................................................................................................ 78
10.1 External Filter Components .......................................................................................................... 78
10.1.1 General ................................................................................................................................ 78
10.1.2 Jitter Attenuation ................................................................................................................. 80
10.1.3 Capacitor Selection ............................................................................................................. 81
10.1.4 Circuit Board Layout ............................................................................................................ 82
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