CS42526_05 Datasheet, PDF (12/93 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
SWITCHING CHARACTERISTICS
(For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C;
VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C_L = 30 pF)
Parameters
Symbol
RST Pin Low Pulse Width
(Note 12)
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
(Note 14)
RMCK Output Duty Cycle
(Note 15)
OMCK Frequency
(Note 13)
OMCK Duty Cycle
(Note 13)
CX_SCLK, SAI_SCLK Duty Cycle
CX_LRCK, SAI_LRCK Duty Cycle
Master Mode
RMCK to CX_SCLK, SAI_SCLK active edge delay
t_smd
RMCK to CX_LRCK, SAI_LRCK delay
t_lmd
Slave Mode
Min
1
30
-
45
1.024
40
45
45
0
0
Typ
Max
Units
-
-
ms
-
200
kHz
200
-
ps RMS
50
55
%
-
25.600
MHz
50
60
%
50
55
%
50
55
%
-
15
ns
-
15
ns
CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT,
SAI_SDOUT Output Valid
t_dpd
CX_LRCK, SAI_LRCK Edge to MSB Valid
t_lrpd
CX_SDIN Setup Time Before CX_SCLK Rising Edge
t_ds
10
CX_SDIN Hold Time After CX_SCLK Rising Edge
t_dh
30
CX_SCLK, SAI_SCLK High Time
t_sckh
20
CX_SCLK, SAI_SCLK Low Time
t_sckl
20
CX_SCLK, SAI_SCLK falling to CX_LRCK, SAI_LRCK
Edge
t_lrck
-25
-
(Note 16)
ns
-
26.5
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
+25
ns
Notes:
12. After powering-up the CS42526, RST should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 26 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 53 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
CX_SCLK
SAI_SCLK
(output)
CX_LRCK
SAI_LRCK
(output)
RMCK
t _smd
t _lmd
Figure 1. Serial Audio Port Master Mode Timing
CX_LRCK
SAI_LRCK
(input)
CX_SCLK
SAI_SCLK
(input)
t _lrck
t _sckh
tsckl
CX_SDINx
CX_SDOUT
SAI_SDOUT
t_{lrpd tds}
tdh
MSB
tdpd
MSB-1
Figure 2. Serial Audio Port Slave Mode Timing
12
DS585F1