CS5571 Datasheet, PDF (28/32 Pages) Cirrus Logic – ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ΔΣ ADC

6/25/07
14:12
CS5571
BP/UP – Bipolar/Unipolar Select, Pin 11
The BP/UP pin determines the span and the output coding of the converter. When set high to
select BP (bipolar), the input span of the converter is -2.048 volts to +2.048 volts (assuming the
voltage reference is 4.096 volts) and outputs data is coded in two's complement format. When
set low to select UP (unipolar), the input span is 0 to +2.048 and the output data is coded in
binary format.
DITHER – Dither Select, Pin 12
When DITHER is high (DITHER = VL), output conversion words will be dithered. When DITHER
is low (DITHER = VLR), output words will be dominated by quantization.
RST – Reset, Pin 13
Reset is necessary after power is initially applied to the converter. When the RST input is taken
low, the logic in the converter will be reset. When RST is released to go high, certain portions of
the analog circuitry are started. RDY falls when reset is complete.
CAL – Calibrate, Pin 14
After power is applied, a reset should be performed prior to calibration. After an initial reset, cal-
ibration can be performed at any time. Calibration can be initiated in either of two ways. If CAL
is high when coming out of reset, (RST going high), a calibration will be performed. If RST is
taken high with CAL low, a calibration is not performed, but calibration can be initiated by taking
CAL high at any time the converter is idle. RDY will also fall when calibration is completed.
CONV – Convert, Pin 15
The CONV pin initiates a conversion cycle if taken low, unless a calibration cycle or a previous
conversion is in progress. When the conversion cycle is completed, the conversion word is out-
put to the serial port register and the RDY signal goes low. If CONV is held low and remains low
when RDY falls another conversion cycle will be started.
DCR – Digital Core Regulator, Pin 16
DCR is the output of the on-chip regulator for the digital logic core. DCR should be bypassed
with a capacitor to V2-. The DCR pin is not designed to power any external load.
V2+ – Positive Power 2, Pin 17
The V1+ and V2+ pins provide a positive supply voltage to the circuitry of the chip. These two
pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should be
supplied from the same source voltage. For single supply operation these two voltages are
nominally +5 V. For dual supply operation they are nominally +2.5 V.
V2- – Negative Power 2, Pin 18
The V1- and V2- pins provide a negative supply voltage to the circuitry of the chip. These two
pins should be decoupled as shown in the application block diagrams. V1- and V2- should be
supplied from the same source voltage. For single supply operation these two voltages are
nominally 0 V (Ground). For dual supply operation they are nominally -2.5 V.
MCLK – Master Clock, Pin 19
The master clock pin (MCLK) is a multi-function pin. If tied low (MCLK = VLR) the on-chip oscil-
lator will be enabled. If tied high (MCLK = VL), all clocks to the internal circuitry of the converter
will stop. When MCLK is held high the internal oscillator will also be stopped. MCLK can also
function as the input for an external CMOS-compatible clock that conforms to supply voltages
on the VL and VLR pins.
VLR, VL – Logic Interface Power/Return, Pin 20, 21
VL and VLR are the supply voltages for the digital logic interface. VL and VLR can be config-
ured with a wide range of common mode voltage. The following interface pins function from the
VL/VLR supply: SMODE, CS, SCLK, TST, SDO, RDY, DITHER, CONV, RST, CONV, CAL,
BP/UP, and MCLK.
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