CS5571 Datasheet, PDF (27/32 Pages) Cirrus Logic – ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ΔΣ ADC

6/25/07
14:12
CS5571
4. PIN DESCRIPTIONS
Chip Select
Factory Test
Serial Mode Select
Analog Input
Analog Common
Negative Power 1
Positive Power 1
Buffer Enable
Voltage Reference Input
Voltage Reference Input
Bipolar/Unipolar Select
Dither Select
CS 1
TST 2
SMODE 3
AIN 4
ACOM 5
V1- 6
V1+ 7
BUFEN 8
VREF+ 9
VREF- 10
BP/UP 11
DITHER 12
24 RDY
23 SCLK
22 SDO
21 VL
20 VLR
19 MCLK
18 V2-
17 V2+
16 DCR
15 CONV
14 CAL
13 RST
Ready
Serial Clock Input/Output
Serial Data Output
Logic Interface Power
Logic Interface Return
Master Clock
Negative Voltage 2
Positive Voltage 2
Digital Core Regulator
Convert
Calibrate
Reset
CS – Chip Select, Pin 1
The Chip Select pin allows an external device to access the serial port. When held high, the
SDO output will be held in a high-impedance output state.
TST – Factory Test, Pin 2
For factory use only. Tie to VLR.
SMODE – Serial Mode Select, Pin 3
The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or
slave interface.If SMODE is tied high (to VL), the port will operate in the Synchronous
Self-Clocking (SSC) mode. In SSC mode the port acts as a master in which the converter out-
puts both the SDO and SCLK signals. If SMODE is tied low (to VLR) the port will operate in the
Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which
the external logic or microcontroller generates the SCLK used to output the conversion data
word from the SDO pin.
AIN, ACOM – Differential Analog Input, Pin 4, 5
AIN and ACOM are the single-ended input and the analog return for the input signal, respec-
tively.
V1- – Negative Power 1, Pin 6
The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1- and V2- should
be supplied from the same source voltage. For single supply operation these two voltages are
nominally 0 V (Ground). For dual supply operation they are nominally -2.5 V.
V1+ – Positive Power 1, Pin 7
The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should
be supplied from the same source voltage. For single supply operation these two voltages are
nominally +5 V. For dual supply operation they are nominally +2.5 V.
BUFEN – Buffer Enable, Pin 8
Buffers on input pins AIN and ACOM are enabled if BUFEN is connected to V1+ and disabled if
connected to V1-.
VREF+, VREF- – Voltage Reference Input, Pin 9, 10
A differential voltage reference input on these pins functions as the voltage reference for the
converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with
4.096 volts being the nominal reference voltage value.
DS768A5
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