CS4207 Datasheet, PDF (25/144 Pages) Cirrus Logic – Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp

CS4207
If RESET is asserted low, and BITCLK and SYNC are not running at the time (defined as link low power
state), the codec will signal the power state change request and initialization request asynchronously by as-
serting SDI high continuously until it detects the de-assertion of RESET. It will then asynchronously drive
SDI low with the de-assertion of the RESET. With the RESET signal high, the codec will reestablish the con-
nection with the controller by performing a “Codec Initialization request”.
4.4 D3 Lower Power State Support
The D3 low power state allows for, but does not require, the lowest possible power consuming state under
software control, in which Extended Power States Supported (EPSS) requirements can be met. While in
the D3 state, the CS4207 will retain sufficient operational capability to properly respond to subsequent soft-
ware Get/Set Power State commands (Verb ID=F05h/705h) to the Audio Function Group (Node ID = 01h).
In addition, while in the D3 power state, Link Reset and “Double Function Group” reset are supported. All
other Get/Set commands will be ignored while the codec is in the D3 power state.
Widgets reporting an EPSS of ‘1’b will transition from D3 state to D0 state in less than 10 milliseconds (this
is a target). This interval is measured from the response to the Set Power State verb that caused the tran-
sition from D3 back to fully operational D0 state.
It is permissible for the audio fidelity for analog outputs to be slightly degraded if audio playback begins im-
mediately once the fully operational state is entered. However, audio fidelity will not be degraded 75ms after
the transitioning to D0 state.
4.5 Extended Power States Supported (EPSS)
EPSS indicates that the Audio Function Group or a particular Widget supports additional capabilities allow-
ing better low power operation. The CS4207 will report EPSS support at the Function group level and will
enable low power operation for all Input and Output Converter Widgets, and the following pin widgets which
are capable of reporting presence detection:
– Headphone pin widget (node ID 09h)
– Line Out 1 pin widget (node ID 0Ah)
– Line In 1/Mic In 2 pin widget (node ID 0Ch)
– Mic In 1/Line In 2 pin widget (node ID 0Dh)
– S/PDIF Receiver Input pin widget (node ID 0Fh).
The following requirements will also be implemented by each input/output converter widget and the above
listed pin widgets:
• Report PowerCntrl set to ‘1’b and support the Supported Power States verb.
• Jack Presence state change reporting (when enabled) will operate regardless of the Widget and Audio
Function Group power state.
• Reporting of presence state change and issuing system wake when the link clock (BITCLK) is not oper-
ational is supported.
• The S/PDIF Receiver to S/PDIF Transmitter digital loop-through (no clock re-timing) will continue to op-
erate (if enabled) even though any one, or all of the S/PDIF Receiver Input Converter Widget, S/PDIF
Transmitter Output Converter Widget or S/PDIF Receiver Input Pin Widget enters into low power states.
This digital loop-through will also continue to operate if the Audio Function Group is placed in the D3 low
power state, during a Link Reset, and even if the HD Audio BITCLK is stopped.
• Dependencies between converter widgets and associated pin widgets will not cause unexpected results
when one node of the dependency is placed into D3 state. The diagrams and tables below demonstrate
typical audio streams.
DS880F1
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