CS4272-DZZ Datasheet, PDF (24/53 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4272
5. APPLICATIONS
5.1 Stand-Alone Mode
5.1.1 Recommended Power-Up Sequence
1) When using the CS4272 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are
stable. When using the CS4272 with internally generated MCLK, hold RST low until the power supply is stable.
2) Bring RST high. If the internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from
the release of RST.
5.1.2 Master/Slave Mode
The CS4272 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and
SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-
mended that SCLK be 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4272 will default to Slave Mode. Master Mode may be accessed by placing a 47 kΩ
pull-up to VL on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4.
5.1.3 System Clocking
The CS4272 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
Table 1. Speed Modes
Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
4-50 kHz
50-100 kHz
100-200 kHz
5.1.3.1 Crystal Applications (XTI/XTO)
An external crystal may be used in conjunction with the CS4272 to generate the master clock signal. To accomplish
this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as
shown in the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 2.
In this configuration, MCLK is a buffered output and, as shown in the Typical Connection Diagram, nothing other
than the crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the
MCLK pin prior to 1 ms from the release of RST.
Table 2. Crystal Frequencies
Mode
Single Speed
Double Speed
Quad Speed
Crystal Frequency
512 x Fs
256 x Fs
128 x Fs
To operate the CS4272 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven
externally with an appropriate speed clock.
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