CS4272-DZZ Datasheet, PDF (21/53 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4272
SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT
(Inputs: logic 0 = AGND, logic 1 = VL)
Parameter
Symbol
Min
Max
I²C Mode
SCL Clock Frequency.
f_scl
-
100
RST Rising Edge to Start.
t_irs
500
-
Bus Free Time Between Transmissions.
t_buf
4.7
-
Start Condition Hold Time (prior to first clock pulse).
t_hdst
4.0
-
Clock Low time.
t_low
4.7
-
Clock High Time.
t_high
4.0
-
Setup Time for Repeated Start Condition.
t_sust
4.7
-
SDA Hold Time from SCL Falling.
(Note 23)
t_hdd
0
-
SDA Setup time to SCL Rising.
t_sud
250
-
Rise Time of Both SDA and SCL Lines.
t_r
-
1
Fall Time of Both SDA and SCL Lines.
t_f
-
300
Setup Time for Stop Condition.
t_susp
4.7
-
Notes: 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
RST
t _irs
Stop
Start
Repeated
Start
SDA
SCL
t _buf
t _hdst
t _high
t _hdst
tf
t _low t _hdd
t _sud
t _sust
tr
Figure 6. I²C Mode Control Port Timing
Stop
t _susp
DS593F1
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