CS5101A_06 Datasheet, PDF (23/39 Pages) Cirrus Logic – 16-bit, 100 kSps / 20 kSps A/D Converters

CS5101A CS5102A
+5V
R
1N4148
C
VD+ _CS5101A
OR
CS5102A
RST
Figure 10. Power-up Reset Circuit
5.2 Single-channel Operation
The CS5101A and CS5102A can alternatively be
used to sample one channel by tying the CH1/2 in-
put high or low. The unused AIN pin should be tied
to the analog input signal or to AGND. (If operating
in free run mode, AIN1 and AIN2 must be tied to
the same source, as CH1/2 is reconfigured as an
output.)
6. ANALOG CIRCUIT CONNECTIONS
Most popular successive approximation A/D con-
verters generate dynamic loads at their analog
connections. The CS5101A and CS5102A inter-
nally buffer all analog inputs (AIN1, AIN2, VREF,
and AGND) to ease the demands placed on exter-
nal circuitry. However, accurate system operation
still requires careful attention to details at the de-
sign stage regarding source impedances as well
as grounding and decoupling schemes.
6.1 Reference Considerations
An application note titled AN004, Voltage
References for the CS5012A / CS5014 /CS5016 /
CS5101A/ CS5102A / CS5126 Series of A/D Con
verters is available for the CS5101A and
CS5102A. In addition to working through a refer-
ence circuit design example, it offers several built-
and-tested reference circuits.
During conversion, each capacitor of the calibrated
capacitor array is switched between VREF and
AGND in a manner determined by the successive-
approximation algorithm. The charging and dis-
charging of the array results in a current load at the
reference. The CS5101A and CS5102A each in-
clude an internal buffer amplifier to minimize the
external reference circuit's drive requirement and
preserve the reference's integrity. Whenever the
array is switched during conversion, the buffer is
used to coarse-charge the array thereby providing
the bulk of the necessary charge. The appropriate
array capacitors are then switched to the unbuf-
fered VREF pin to avoid any errors due to offsets
and/or noise in the buffer.
The external reference circuitry need only provide
the residual charge required to fully charge the ar-
ray after coarse-charging from the buffer. This cre-
ates an ac current load as the CS5101A and
CS5102A sequence through conversions. The ref-
erence circuitry must have a low enough output im-
pedance to drive the requisite current without
changing its output voltage significantly. As the an-
alog input signal varies, the switching sequence of
the internal capacitor array changes. The current
load on the external reference circuitry thus varies
in response with the analog input. Therefore, the
external reference must not exhibit significant
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output imped-
ance at the high end of the frequency spectrum,
while almost all precision references exhibit ex-
tremely low output impedance at DC. The pres-
ence of large capacitors on the output of some
voltage references, however, may cause peaking
in the output impedance at intermediate frequen-
cies. Care should be exercised to ensure that sig-
nificant peaking does not exist or that some form of
compensation is provided to eliminate the effect.
The magnitude of the current load on the external
reference circuitry will scale to the master clock fre-
quency. At the full-rated 9.216 MHz clock
(CS5101A), the reference must supply a maximum
load current of 20 µA peak-to-peak (2 µA typical).
An output impedance of 2 Ω will therefore yield a
maximum error of 40 µV. At the full-rated 2.0 MHz
clock (CS5102A), the reference must supply a
maximum load current of 5 µA peak-to-peak
(0.5µA typical). An output impedance of 2 Ω will
therefore yield a maximum error of 10.0 µV. With a
4.5 V reference and LSB size of 138 µV this would
ensure approximately 1/14 LSB accuracy. A 10 µF
DS45F6
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