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CS5101A_06 Datasheet, PDF (22/39 Pages) Cirrus Logic – 16-bit, 100 kSps / 20 kSps A/D Converters | |||
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CS5101A CS5102A
5. SYSTEM DESIGN USING THE CS5101A & CS5102A
Figure 9 shows a general system connection diagram for the CS5101A and CS5102A.
+5VA
+
10
+
4.7 µ F 0.1 µ F
0.1 µ F 1 µ F
25
VA+
26
7
TST V D +
XOUT 4
VD+
M ode Control
Voltage Reference
18 O U T M O D
27 S C K M O D
17 B P /U P
16
CODE
CS5101A
OR
20 V R E F C S5102A
22
AGND
XTAL
CLKIN 3
10 M
2
RST
28
SLEEP
5
STBY
13
CH1/2
C R S /F IN 10
H O L D 12
C o n tro l
Logic
A n a lo g
Sources
50
*
1 nF
50
*
1 nF
19
A IN 1
CN0PGO
24 A IN 2
CN0PGO
* For best dynamic
S/(N+D) perform ance.
21 R E F B U F
8
TRK1
9
TRK2
11
S S H /S D L
S C L K 14
S D A T A 15
DGND 6
D a ta
In te rfa c e
C1
C2 = C1
EXT
CLOCK
XTAL & C1 Table
CS5101A
FRN
XTAL
8.0 M Hz
C1, C2
10 pF
PDT, RBT,
SSC
8.192 M Hz
10 pF
CS5102A
FRN
PDT, RBT,
SSC
1.6 M Hz
1.6 M Hz
or
2.0 M Hz
30 pF
30 pF
-5VA
0.1 µ F
VA-
VD-
23
1
10
Unused Logic inputs should
be tied to VD+ or DG ND.
+ 4.7 µ F
0.1 µ F
0.1 µ F + 1 µ F
Figure 9. CS5101A/CS5102A System Connection Diagram
5.1 System Initialization
Upon power up, the CS5101A and CS5102A must
be reset to guarantee a consistent starting condi-
tion and to initially calibrate the device. Due to
each device's low power dissipation and low tem-
perature drift, no warm-up time is required before
reset to accommodate any self-heating effects.
However, the voltage reference input should have
stabilized to within 0.25% of its final value before
RST rises to guarantee an accurate calibration.
Later, the CS5101A and CS5102A may be reset at
any time to initiate a single full calibration.
When RST is brought low all internal logic clears.
When RST returns high on the CS5101A, a cali-
bration cycle begins which takes 11,528,160 mas-
ter clock cycles to complete (approximately
1.4 seconds with an 8 MHz master clock). The cal-
ibration cycle on the CS5102A takes 2,882,040
master clock cycles to complete (approximately
1.8 seconds with a 1.6 MHz master clock). The
CS5101A's and CS5102A's STBY output remains
low throughout the calibration sequence, and a ris-
ing transition indicates the device is ready for nor-
mal operation. While calibrating, the CS5101A and
CS5102A will ignore changes on the HOLD input.
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and ca-
pacitor as shown in Figure 10. The resistor should
be less than or equal to 10 kâ¦. The system power
supplies, voltage reference, and clock should all be
established prior RST rising.
22
DS45F6
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