CS4205 Datasheet, PDF (21/80 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with Portable Computing

CS4205
4.1.3 Command Data Port (Slot 2)
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved
WD[15:0]
Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac-
cess is a read, this slot is ignored.
NOTE:
For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means
that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output Slot 0 should
always be ‘set’ during the same audio frame. No write access may be split across 2 frames.
4.1.4 PCM Playback Data (Slots 3-11)
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD[19:0]
Playback Data. The PD[19:0] bits contain the 20-bit PCM (2’s complement) playback data for
the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 14 on page 42
lists a cross reference for each function and its respective slot. The mapping of a given slot
to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the ID[1:0]
bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0] and AMAP bits in the
AC Mode Control Register (Index 5Eh).
4.1.5 GPIO Pin Control (Slot12)
Bit 19 18 17 16 15 14 13 12 11 10 9 8
7
6
5
4 3210
Not Implemented
GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Reserved
GPIO[4:0]
GPIO Pin Control. The GPIO[4:0] bits control the CS4205 GPIO pins configured as outputs.
Write accesses using GPIO pin control bits configured at outputs will be reflected on the GPIO
pin output on the next AC-link frame. Write accesses using GPIO pin control bits configured
as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Control Reg-
ister (Index 60h) is ‘set’, the bits in output Slot 12 are ignored and GPIO pins configured as
outputs are controlled through the GPIO Pin Status Register (Index 54h).
DS489PP2
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