CS4373A Datasheet, PDF (20/34 Pages) Cirrus Logic – Low-power, High-performance Test DAC

CS4373A
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIG-
So the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 V_pp differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 V_pp differ-
ential signal centered on a -0.15 V common
mode voltage never exceeds +1.1 V with re-
spect to ground and never drops below -1.4 V
with respect to ground on either half. By defini-
tion, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would read 1.767 V_rms, or 5 V_pp.
5.2.2 AC Common Mode
The final AC test mode (MODE 6) creates a
matched AC common mode analog signal for
CMRR testing of the measurement channel. In
mode 6, both sets of analog outputs (OUT and
BUF) are enabled. There is no common mode
AC waveform output for an attenuator setting
of 1/64.
OUT+
OUT-
CS4373A
MODE 6
BUF+
BUF-
Maximum
2.5 Vpp
Common
Mode
Maximum
2.5 Vpp
Common
Mode
Figure 9. AC Common Mode
Gross leakage in the sensor channel can be
detected by applying a full-scale AC common
mode signal. If there is a significant differential
mismatch in the channel due to sensor leak-
age, the AC common mode signal will be con-
verted to a measurable differential signal at
the fundamental frequency.
5.2.3 AC Stability
For the CS4373A low-power ∆Σ architecture to
remain stable, the TDATA input bit stream
should only encode 100 Hz or lower band-
width analog signals. For TDATA bit stream
frequencies above 100 Hz (for example, TBS
impulse mode), the encoded amplitude must
be reduced -20 dB below full scale to guaran-
tee stability.
If the CS4373A low-power ∆Σ architecture be-
comes unstable, persistent elevated noise will
be present on the analog outputs and AC lin-
earity will be poor. To recover stability, place
the CS4373A into power down or sleep mode
and restart the CS5376A test bit stream gener-
ator before placing the CS4373A back into an
AC test mode.
5.3 DC Test Modes
DC test modes create precision level-shifted
and buffered versions of the voltage reference
input as precision DC common mode and DC
differential analog outputs. The absolute accu-
racy of the DC test modes is highly dependent
on the absolute accuracy of the voltage refer-
ence input voltage.
5.3.1 DC Common Mode
The first DC test mode (MODE 4) creates a
matched DC common mode analog output
voltage as a baseline measurement for gain
calibration and differential pulse tests. In mode
4, both sets of analog outputs (OUT and BUF)
are enabled.
5.3.2 DC Differential
The second DC test mode (MODE 5) creates
a precision differential DC analog output volt-
age as the final measurement for gain calibra-
tion and as the step/pulse output for
differential pulse tests. In mode 5, both sets of
analog outputs (OUT and BUF) are enabled.
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