CS4373A Datasheet, PDF (13/34 Pages) Cirrus Logic – Low-power, High-performance Test DAC

CS4373A
DIGITAL CHARACTERISTICS (CONT.)
Parameter
Symbol Min
Master Clock
MCLK Frequency
MCLK Period
MCLK Duty Cycle
MCLK Rise Time
MCLK Fall Time
MCLK Jitter (In-band or aliased in-band)
MCLK Jitter (Out-of-band)
Master Sync
(Note 25) f_CLK
-
(Note 25) t_mclk
-
(Note 8) MCLK_DC
40
(Note 8) t_RISE
-
(Note 8) t_FALL
-
(Note 8) MCLK_IBJ
-
(Note 8) MCLK_OBJ
-
MSYNC Setup Time to MCLK rising
(Note 8, 26) t_mss
20
MSYNC Period
(Note 8, 26) t_msync
40
MSYNC Hold Time after MCLK falling
(Note 8, 26) t_msh
20
MSYNC Instant to TDATA Start
(Note 8, 27) t_tdata
-
Typ
2.048
488
-
-
-
-
-
122
976
122
1220
Max
-
-
60
50
50
300
1
-
-
-
-
Unit
MHz
ns
%
ns
ns
ps
ns
ns
ns
ns
ns
Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters
a power-down state.
26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization
instant (t₀) on next MCLK rising edge.
27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing
diagram shows no TBSDATA delay.
DS699F2
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