WM8234 Datasheet, PDF (18/144 Pages) Wolfson Microelectronics plc – 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output

WM8234
CIN _IN*
VRLC/
VBIAS
CLAMP
RLC switch
VSMP
VSMP (if CDS=0)
RSMP (if CDS=1)
VSMP
'Video'
sample
capacitor
CONTROL
INTERFACE
CLAMP
VSMP (if CDS=0)
RSMP (if CDS=1)
'Reference'
sample
capacitor
5-BIT
RLCDAC
VRLC_VSEL[4:0]
VRLCEN
Figure 10 RLC Clamp Control Options
INPUT VIDEO
SIGNAL
Pixel counter
VSMP
RSMP
CLAMP
RLC switch control
"CLAMP"
In CDS operation, when an input waveform has a stable reference level on every pixel, it may be
desirable to clamp every pixel during this period. Setting CLAMP=high means that the RLC switch is
closed whenever the RSMP is high, as shown in Figure 11.
In non-CDS operation, setting CLAMP=high means that the RLC switch is closed whenever the VSMP
is high, as shown in Figure 12.
reference
("black") level
video level
Video sample taken on
fallling edge of VSMP
Reset/reference sample taken
on fallling edge of RSMP
RLC switch closed
when RSMP=1
Figure 11 Reset Level Clamp Operation, CDS Operation Shown
INPUT VIDEO
SIGNAL
Pixel counter
VSMP
CLAMP
RLC switch control
"CLAMP"
Video sample taken on
fallling edge of VSMP
video level
RLC switch closed
when VSMP=1
Figure 12 Line Clamp Operation, non-CDS operation shown
18
Rev 4.6