CS62180 Datasheet, PDF (17/50 Pages) Cirrus Logic – T1 FRAMER

CS62180B
inputs all other DL bits on TLINK using
TLCLK.
Note: When using internal S-bit generation
(TCR.2 = 0) in conjunction with external F_T bit
insertion (TCR.6 = 1), the CS62180B
will logically ’OR’ the value at TSER
with the internally generated value. This means
that the data on TSER during S-bit periods
should always be "0" to avoid corrupting the
generated F_S pattern.
Transmit Idle Code Select
TCR.3: TIS
Individual DS0 channels can be replaced with
idle codes by setting the corresponding bits in
the Transmit Idle Registers (TIR1 - TIR3) de-
scribed below. TIS (TCR.3) selects which of two
codes to use. A "0" in TCR.3 will cause a 7F
(hex) to be inserted into the channels specified in
the TIR. Setting TCR.3 to a "1" will select an FF
(hex) code. By asserting all 24 channels idle in
the TIR, this setting can be used to generate a
"framed" blue alarm. Whichever mode is se-
lected, bit-robbed signaling will still effect idle
channels unless they are programmed clear (see
Transmit Transparent Registers, below).
Robbed Bit Signaling Enable
TCR.4: RBSE
A "0" in RBSE (TCR.4) will disable bit-robbed
signaling. Setting TCR.4 to a "1" will enable sig-
naling in all channels. In this mode, data on
TABCD is inserted into the LSB of all DS0
channels during signaling frames. For mixed
voice and data transmission, individual DS0
channels can be programmed clear by setting the
corresponding bits in the Transmit Transparent
Registers (TTR1 - TTR3) described below.
CRC Pass-through
TCR.5: TCP
In 193E framing mode, the CRC bits (F-bit of
frames 2, 6, 10, 14, 18, and 22) may be either
generated internally, or supplied by the user.
Clearing TCP (TCR.5) causes the CS62180B
to generate and insert the CRC bits
automatically. If TCR.5 is set to a "1", data
for the CRC channel may be externally supplied.
When using this mode, CRC bits are sampled
from TSER, and must be externally multiplexed
into the DS0 channel data at the F-bit times of
CRC frames.
F_T/FPS Pass Through
TCR.6: TFPT
When TFPT (TCR.6) is clear, the framing bits
for 193S, T1DM and SLC-96^® (F_T), or 193E
(FPS) are generated internally and automatically
inserted into the outgoing data stream. Setting
TCR.6 to a "1" allows the framing bits to be ex-
ternally provided. When using this mode,
framing bits are sampled from TSER, and must
be externally multiplexed into the DS0 channel
data at the F-bit times of the appropriate frames.
See note under TCR.2, above.
Output Data Format
TCR.7: ODF
ODF (TCR.7) allows the format of the output
data at TPOS/TNEG to be set to either dual-
unipolar or NRZ format. Clearing TCR.7 selects
for dual-unipolar format on TPOS/TNEG. Set-
ting TCR.7 to a "1" causes data to be output on
TPOS in NRZ format, and TNEG is held low.
When operating in hardware mode, output de-
faults to the dual-unipolar format. TPOS and
TNEG may not be tied together, so an external
OR gate is recommended if NRZ is required
while in hardware mode.
DS225PP2
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