CS5376A Datasheet, PDF (17/107 Pages) Cirrus Logic – LOW POWER MULTI CHANNEL DECIMATION FILTER

SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, and MDATAx
SYNC
CS5376A
MCLK
MSYNC
MDATAx
t_msd
t_msh
t_msd
Data1
Data2
Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.
f_MCLK
t_msd = T_MCLK / 4
t_msh = T_MCLK
2.048 MHz
t_msd = 122 ns
t_msh = 488 ns
1.024 MHz
t_msd = 244 ns
t_msh = 976 ns
Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing
Parameter
Master Clock Frequency
Master Clock Duty Cycle
Master Clock Rise Time
Master Clock Fall Time
Master Clock Jitter
Synchronization after SYNC rising
MSYNC Setup Time to MCLK rising
MCLK rising to Valid MDATA
MSYNC falling to MCLK rising
Symbol Min
Typ
Max Unit
(Note 3) CLK
32 32.768 33
MHz
DTY
40
-
60
%
t_RISE
-
t_FALL
-
JTR
-
-
20
ns
-
20
ns
-
300
ps
(Note 4) SYNC
-2
-
2
µs
t_msr
20
-
-
ns
t_mdv
-
-
75
ns
t_msf
20
-
-
ns
Notes: 3. Master clock frequencies above or below 32.768 MHz will affect generated clock frequencies.
4. Sampling synchronization between multiple CS5376A devices receiving identical SYNC signals.
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