CS5376A Datasheet, PDF (1/107 Pages) Cirrus Logic – LOW POWER MULTI CHANNEL DECIMATION FILTER

CS5376A
Low Power Multi-Channel Decimation Filter
Features
1 to 4 Channel Digital Decimation Filter
Multiple On-Chip FIR and IIR Coefficient Sets
Programmable Coefficients for Custom Filters
Synchronous Operation
Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 250 SPS
200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS
Digital Gain and Offset Corrections
Test DAC Bit Stream Generator
Sine Wave or Impulse Output Mode
Time Break Controller, General Purpose I/O
Secondary SPI Port, Boundary Scan JTAG
Microcontroller or EEPROM Configuration
Small Footprint 64-pin TQFP Package
Low Power Consumption
9 mW per Channel at 500 SPS
Flexible Power Supplies
I/O Interface: 3.3 V or 5.0 V
Digital Logic Core: 3.0 V, 3.3 V or 5.0 V
I
Description
The CS5376A is a multi-function digital filter utilizing a
low-power signal processing architecture to achieve effi-
cient filtering for up to four ∆Σ modulators. By combining
the CS5376A with CS3301/02 differential amplifiers,
CS5371/72 ∆Σ modulators, and the CS4373 ∆Σ test
DAC a synchronous high resolution multi-channel mea-
surement system can be designed quickly and easily.
Digital filter coefficients for the CS5376A FIR and IIR fil-
ters are included on-chip for a simple setup, or they can
be programmed for custom applications. Selectable dig-
ital filter decimation ratios produce output word rates
from 4000 SPS to 1 SPS, resulting in measurement
bandwidths ranging from 1600 Hz down to 400 mHz
when using the on-chip coefficient sets.
The CS5376A includes integrated peripherals to simplify
system design: offset and gain corrections, a test DAC
bit stream generator, a time break controller, 12 general
purpose I/O pins, a secondary SPI port, and a boundary
scan JTAG port.
ORDERING INFORMATION
CS5376A-IQ -40 to +85 ^oC
64-pin TQFP
S erial Da ta O utput P ort
Decim ation and
Filte ring E ngine
JTAG
Interface
M odulator Data
Inte rfa ce
Clock and
S ynchronization
SPI 1
Serial P eripheral Interface 1
Tim e B reak C ontrolle r
Test B it S tre am C ontroller
G PIO
General P urpose I/O
SPI 2
Serial P eripheral Interface 2
CLK
SYNC
M CLK
M SYNC
SSI
SCK1
M IS O
M OSI
SINT
T IM E B
T B SC L K
T B SD AT A
G P IO 1 1:E E C S
G P IO 1 0
G P IO 9
G P IO 8
G P IO 7
G P IO 6
G P IO 5
G P IO 4 :C S 4
G P IO 3 :C S 3
G P IO 2 :C S 2
G P IO 1 :C S 1
G P IO 0 :C S 0
SCK2
SO
SI1
SI2
SI3
SI4
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© Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
FEB ‘04
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